2.9 Axcelerator Clock Management System

Each member of the Axcelerator family^⁶ contains eight Phase-Locked Loop (PLL) blocks, which perform the following functions:

Programmable Delay (32 steps of 250 ps)
Clock Skew Minimization
Clock Frequency Synthesis

Each PLL has the following key features:

Input Frequency Range: 14 to 200 MHz
Output Frequency Range: 20 MHz to 1 GHz
Output Duty Cycle Range: 45% to 55%
Maximum Long-Term Jitter: 1% or 100ps (whichever is greater)
Maximum Short-Term Jitter: 50ps + 1% of Output Frequency
Maximum Acquisition Time (lock): 20μs

¹

AX2000-CQ256 does not support operation of the Phase-Locked Loops. This is in order to support full pin compatibility with RTAX2000S/SL-CQ256.

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