2.6.2 Carry-Chain Logic

The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance.

To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (that is, carry out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay from the FCI (that is, carry in) into the two-bit Cluster. The two-bit carry logic is shown in the following figure.

The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one C-cell pair, drives the FCI input of the C-cell pair immediately below it (see Figure 1-4 and Figure 2-31).

The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through Microchip's macro library.

The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns.

The following figure shows the two-bit carry logic of Axcelerator device.

Figure 2-30. Axcelerator’s Two-Bit Carry Logic

The following figure shows carry-chain sequencing of C-Cells.

Figure 2-31. Carry-Chain Sequencing of C-Cells