2.4.1.2 Timing Characteristics

The following table lists the timing characteristics of 2.5V GTL+.

Table 2-43. 2.5V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70 °C
ParameterDescription–2 Speed–1 SpeedStd SpeedUnits
Min.Max.Min.Max.Min.Max.
2.5V GTL+ I/O Module Timing
tDPInput buffer1.711.952.29ns
tPYOutput buffer1.131.291.52ns
tICLKQClock-to-Q for the I/O input register0.670.770.90ns
tOCLKQClock-to-Q for the I/O output register and the I/O enable register0.670.770.90ns
tSUDData input set-up0.230.270.31ns
tSUEEnable input set-up0.260.300.35ns
tHDData input hold0.000.000.00ns
tHEEnable input hold0.000.000.00ns
tCPWHLClock pulse width high to low0.390.390.39ns
tCPWLHClock pulse width low to high0.390.390.39ns
tWASYNAsynchronous pulse width0.370.370.37ns
tREASYNAsynchronous recovery time0.130.150.17ns
tHASYNAsynchronous removal time0.000.000.00ns
tCLRAsynchronous Clear-to-Q0.230.270.31ns
tPRESETAsynchronous Preset-to-Q0.230.270.31ns

The following table lists the timing characteristics of 3.3V GTL+.

Table 2-44. 3.3V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70 °C
ParameterDescription–2 Speed–1 SpeedStd SpeedUnits
Min.Max.Min.Max.Min.Max.
3.3V GTL+I/O Module Timing
tDPInput buffer1.711.952.29ns
tPYOutput buffer1.131.291.52ns
tICLKQClock-to-Q for the I/O input register0.670.770.90ns
tOCLKQClock-to-Q for the I/O output register and the I/O enable register0.670.770.90ns
tSUDData input set-up0.230.270.31ns
tSUEEnable input set-up0.260.300.35ns
tHDData input hold0.000.000.00ns
tHEEnable input hold0.000.000.00ns
tCPWHLClock pulse width high to low0.390.390.39ns
tCPWLHClock pulse width low to high0.390.390.39ns
tWASYNAsynchronous pulse width0.370.370.37ns
tREASYNAsynchronous recovery time0.130.150.17ns
tHASYNAsynchronous removal time0.000.000.00ns
tCLRAsynchronous Clear-to-Q0.230.270.31ns
tPRESETAsynchronous Preset-to-Q0.230.270.31ns