54.6 Rev G - 04/2015

Ordering Information	Added Device Identification.
I/O Multiplexing and Considerations	New sections added: SERCOM I²C Pins: Information moved from the "Type" column in Table 6-2 into separate table. Updated CCL column. GPIO Clusters: Moved from Absolute Maximum Ratings. TCC Configurations: Moved from Timer/Counter for Control Applications (TCC).
Memories	Updated Table 9-4. Updated Table 9-1.
PAC - Peripheral Access Controller	Register bit correction: INTFLAGAHB, INTFLAGA, INTFLAGB, INTFLAGC, STATUSA, STATUSB and STATUSC
DSU - Device Service Unit	Table 13-6 updated: MBIST is not available when the device is protected from the external address space.
GCLK - Generic Clock Controller	Block Diagram: GCLK_MAIN goes into the MCLK, not the PM. Signal Description: Available signals are GCLK_IO[7:0].
MCLK – Main Clock	Updated block diagram in Selecting the Synchronous Clock Division Ratio.
OSCCTRL – Oscillators Controller	Added OSC48M Calibration (CAL48M) register added (only available for Rev D silicon).
SUPC – Supply Controller	Updated VREF.SEL bit selection table. Removed references to BODCORE register and bit descriptions and updated description in VDDCORE Brown-Out Detector (BODCORE).
PM - Power Manager	Sleep modes: Removed references to IDLE0 and IDLE1. Renamed IDLE2 to IDLE.
DMAC – Direct Memory Access Controller	CTRL.CRCENABLE bit added in bit position 2.
NVMCTRL – Nonvolatile Memory Controller	CTRLB.CACHEDIS: Updated from one bit in postion 18 to two bits in position 19:18. Updated bit description and bit value settings.
SERCOM SPI – SERCOM Serial Peripheral Interface	Features: Updated references to serial clock speed in master and slave operation.
CAN - Control Area Network (SAM C21 Only)	CREL: Updated reset value from 0x31000000 (device rev B) to 0x32100000 (device rev C and newer).
Timer/Counter (TC)	Added register property "Write-Synchronized" to the CCBUFx and PERBUF registers.
Timer/Counter for Control Applications (TCC)	Updated number of TCC instances from one to three. Counter Operation: 'Stop Command and Event Action' split into 'Stop Command' and 'Pause Event Action' Capture Operations: Value 0 in CAPTMIN mode is captured only in down-counting mode. Ramp Operations: RAMP2C Operation added. Compare Operations: Reorganization of section. Corrected bit names in the WAVE register: CIRCCENx -> CICCENx and CIRPEREN -> CIPEREN.
Configurable Custom Logic (CCL)	Number of LUTCTRL registers changed from eight to four. Number of SEQCTRL registers changed from four to two. Truth Table Inputs Selection: Updated description and figure in Analog Comparator Inputs (AC).
SDADC – Sigma-Delta Analog-to-Digital Converter (SAM C21 only)	Resolution corrected from 24-bit to 16-bit. Conversion range updated from "0V to V_ref"to "0V to 0.7xV_ref" Test Mode section removed. Updated operation formula in the following registers: OFFSETCORR GAINCORR SHIFTCORR Updated RESULT bit description in RESULT.
AC – Analog Comparators	COMPCTRL: SPEED bit description updated. Values 0x1 and 0x2 is reserved.
DAC – Digital-to-Analog Converter (SAM C21 only)	Updated DATA register: DATA bits access corrected from read/write (R/W) to write (W).TPUBSAMD-354
TSENS – Temperature Sensor	Measurement: Added temperature measurement recommendation to avoid discrepancies.
Electrical Characteristics 85°C (SAM C20/C21 E/G/J)	Added electrical characteristics for 85°C. GPIO Clusters moved to I/O Multiplexing and Considerations.
Electrical Characteristics 105°C (SAM C20/C21 E/G/J)	Added electrical characteristics for 105°C.
Packaging Information	Updated package drawings to include GPC, drawing no. and revision letter.
Errata SAM C20 and Errata SAM C21	Updated revision B errata: Added Errata reference 14497, 14633 and 15342. Added revision C errata. Added revision D errata.

Ordering Information

Added Device Identification.

I/O Multiplexing and Considerations

New sections added:

SERCOM I²C Pins: Information moved from the "Type" column in Table 6-2 into separate table.
Updated CCL column.
GPIO Clusters: Moved from Absolute Maximum Ratings.
TCC Configurations: Moved from Timer/Counter for Control Applications (TCC).

Memories

Updated Table 9-4.
Updated Table 9-1.

PAC - Peripheral Access Controller

Register bit correction: INTFLAGAHB, INTFLAGA, INTFLAGB, INTFLAGC, STATUSA, STATUSB and STATUSC

DSU - Device Service Unit

Table 13-6 updated: MBIST is not available when the device is protected from the external address space.

GCLK - Generic Clock Controller

Block Diagram: GCLK_MAIN goes into the MCLK, not the PM.
Signal Description: Available signals are GCLK_IO[7:0].

MCLK – Main Clock

Updated block diagram in Selecting the Synchronous Clock Division Ratio.

OSCCTRL – Oscillators Controller

Added OSC48M Calibration (CAL48M) register added (only available for Rev D silicon).

SUPC – Supply Controller

Updated VREF.SEL bit selection table.
Removed references to BODCORE register and bit descriptions and updated description in VDDCORE Brown-Out Detector (BODCORE).

PM - Power Manager

Sleep modes: Removed references to IDLE0 and IDLE1. Renamed IDLE2 to IDLE.

DMAC – Direct Memory Access Controller

CTRL.CRCENABLE bit added in bit position 2.

NVMCTRL – Nonvolatile Memory Controller

CTRLB.CACHEDIS: Updated from one bit in postion 18 to two bits in position 19:18. Updated bit description and bit value settings.

SERCOM SPI – SERCOM Serial Peripheral Interface

Features: Updated references to serial clock speed in master and slave operation.

CAN - Control Area Network (SAM C21 Only)

CREL: Updated reset value from 0x31000000 (device rev B) to 0x32100000 (device rev C and newer).

Timer/Counter (TC)

Added register property "Write-Synchronized" to the CCBUFx and PERBUF registers.

Timer/Counter for Control Applications (TCC)

Updated number of TCC instances from one to three.
Counter Operation: 'Stop Command and Event Action' split into 'Stop Command' and 'Pause Event Action'
Capture Operations: Value 0 in CAPTMIN mode is captured only in down-counting mode.
Ramp Operations: RAMP2C Operation added.
Compare Operations: Reorganization of section.
Corrected bit names in the WAVE register: CIRCCENx -> CICCENx and CIRPEREN -> CIPEREN.

Configurable Custom Logic (CCL)

Number of LUTCTRL registers changed from eight to four.
Number of SEQCTRL registers changed from four to two.
Truth Table Inputs Selection: Updated description and figure in Analog Comparator Inputs (AC).

SDADC – Sigma-Delta Analog-to-Digital Converter (SAM C21 only)