34.8.35 Tx Buffer Configuration

This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.

Note: Be aware that the sum of TFQS and NDTB may not be greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
Name: TXBC
Offset: 0xC0
Reset: 0x00000000
Property: Write-restricted

Bit 3130292827262524 
  TFQMTFQS[5:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
   NDTB[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
 TBSA[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TBSA[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 30 – TFQM Tx FIFO/Queue Mode

ValueDescription
0 Tx FIFO operation.
1 Tx Queue operation.

Bits 29:24 – TFQS[5:0] Transmit FIFO/Queue Size

ValueDescription
0 No Tx FIFO/Queue.
1 - 32 Number of Tx Buffers used for Tx FIFO/Queue.
>32 Values greater than 32 are interpreted as 32.

Bits 21:16 – NDTB[5:0] Number of Dedicated Transmit Buffers

ValueDescription
0 No Tx FIFO/Queue.
1 - 32 Number of Tx Buffers used for Tx FIFO/Queue.
>32 Values greater than 32 are interpreted as 32.

Bits 15:0 – TBSA[15:0] Tx Buffers Start Address

Start address of Tx Buffers section in Message RAM. When the CAN module addresses the Message RAM it addresses 32-bit words, not single bytes. The configurable start addresses are 32-bit word addresses, i.e. only bits 15 to 2 are evaluated, the two least significant bits are ignored. Bits 1 to 0 will always be read back as “00”.