34.8.13 Error Counter

Note: When CCCR.ASM is set, the CAN protocol controller does not increment TECand REC when a CAN protocol error is detected, but CEL is still incremented.
Name: ECR
Offset: 0x40
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CEL[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RPREC[6:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 TEC[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 23:16 – CEL[7:0] CAN Error Logging

The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.

Bit 15 – RP Receive Error Passive

Bits 14:8 – REC[6:0] Receive Error Counter

Actual state of the Receive Error Counter, values between 0 and 127.

Bits 7:0 – TEC[7:0] Transmit Error Counter

Actual state of the Transmit Error Counter, values between 0 and 255.