34.8.4 Data Bit Timing and Prescaler
This register is write-restricted and only writable if bit fields CCCR.CCE = 1 and CCCR.INIT = 1.
The CAN bit time may be programmed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 GCLK_CAN periods. tq = (DBRP + 1) mtq.
Note:
With a GCLK_CAN of 8MHz, the reset value 0x00000A33 configures the CAN for a fast bit rate of 500 kBits/s.
The bit rate configured for the CAN FD data phase via DBTP must be higher or equal to the bit rate configured for the arbitration phase via NBTP.
| Name: | DBTP |
| Offset: | 0x0C |
| Reset: | 0x00000A33 |
| Property: | Write-restricted |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TDC | DBRP[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DTSEG1[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 0 | 1 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DTSEG2[3:0] | DSJW[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | |
Bit 23 – TDC Transceiver Delay Compensation
| Value | Description |
|---|---|
| 0 | Transceiver Delay Compensation disabled. |
| 1 | Transceiver Delay Compensation enabled. |
Bits 20:16 – DBRP[4:0] Data Baud Rate Prescaler
| Value | Description |
|---|---|
| 0x00 - 0x1F | The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. |
Bits 12:8 – DTSEG1[4:0] Fast time segment before sample point
| Value | Description |
|---|---|
| 0x00 - 0x1F | Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. |
Bits 7:4 – DTSEG2[3:0] Data time segment after sample point
| Value | Description |
|---|---|
| 0x0 - 0xF | Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. DTSEG2 is Phase_Seg2. |
Bits 3:0 – DSJW[3:0] Data (Re)Syncronization Jump Width
| Value | Description |
|---|---|
| 0x0 - 0xF | Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. |