20.8.14 DPLL Control B

Name: DPLLCTRLB
Offset: 0x24
Reset: 0x00
Property: Enable-Protected, PAC Write-Protection

Bit 3130292827262524 
      DIV[10:8] 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
 DIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
    LBYPASS LTIME[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
   REFCLK[1:0]WUFLPENFILTER[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 26:16 – DIV[10:0] Clock Divider

These bits set the XOSC clock division factor and can be calculated with following formula:

f D I V = f X O S C 2 x ( D I V + 1 )

Bit 12 – LBYPASS Lock Bypass

ValueDescription
0 DPLL Lock signal drives the DPLL controller internal logic.
1 DPLL Lock signal is always asserted.

Bits 10:8 – LTIME[2:0] Lock Time

These bits select the lock time-out value:

ValueNameDescription
0x0 Default No time-out. Automatic lock.
0x1 Reserved
0x2 Reserved
0x3 Reserved
0x4 8MS Time-out if no lock within 8ms
0x5 9MS Time-out if no lock within 9ms
0x6 10MS Time-out if no lock within 10ms
0x7 11MS Time-out if no lock within 11ms

Bits 5:4 – REFCLK[1:0] Reference Clock Selection

Write these bits to select the DPLL clock reference:

ValueNameDescription
0x0 XOSC32K XOSC32K clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK GCLK clock reference
0x3 Reserved

Bit 3 – WUF Wake Up Fast

ValueDescription
0 DPLL clock is output after startup and lock time.
1 DPLL clock is output after startup time.

Bit 2 – LPEN Low-Power Enable

ValueDescription
0 The low-power mode is disabled. Time to Digital Converter is enabled.
1 The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power consumption but increase the output jitter.

Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection

These bits select the DPLL filter type:

ValueNameDescription
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter