20.8.4 Status

Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     DPLLLDRTODPLLLTODPLLLCKFDPLLLCKR 
Access RRRR 
Reset 0000 
Bit 76543210 
    OSC48MRDY CLKSWCLKFAILXOSCRDY 
Access RRRR 
Reset 0000 

Bit 11 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete

ValueDescription
0 DPLL Loop Divider Ratio Update Complete not detected.
1 DPLL Loop Divider Ratio Update Complete detected.

Bit 10 – DPLLLTO DPLL Lock Timeout

ValueDescription
0 DPLL Lock time-out not detected.
1 DPLL Lock time-out detected.

Bit 9 – DPLLLCKF DPLL Lock Fall

ValueDescription
0 DPLL Lock fall edge not detected.
1 DPLL Lock fall edge detected.

Bit 8 – DPLLLCKR DPLL Lock Rise

ValueDescription
0 DPLL Lock rise edge not detected.
1 DPLL Lock fall edge detected.

Bit 4 – OSC48MRDY OSC48M Ready

ValueDescription
0 OSC48M is not ready.
1 OSC48M is stable and ready to be used as a clock source.

Bit 2 – CLKSW XOSC Clock Switch

ValueDescription
0 XOSC is not switched and provides the external clock or crystal oscillator clock.
1 XOSC is switched and provides the safe clock.

Bit 1 – CLKFAIL XOSC Clock Failure

Note: Once a first failure has been detected, it is logged in INTFLAG.CLKFAIL and will trigger an interrupt if enabled. After the detection of the first failure, the value of the STATUS.CLKFAIL bit becomes irrelevant and should be ignored until the XOSC clock is restored.
ValueDescription
0 No XOSC failure detected.
1 A XOSC failure was detected.

Bit 0 – XOSCRDY XOSC Ready

ValueDescription
0 XOSC is not ready.
1 XOSC is stable and ready to be used as a clock source.