17.8.7 APBA Mask
| Name: | APBAMASK |
| Offset: | 0x14 |
| Reset: | 0x00000FFF |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSENS | FREQM | EIC | RTC | WDT | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GCLK | SUPC | OSC32KCTRL | OSCCTRL | RSTC | MCLK | PM | PAC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 12 – TSENS TSENS APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the TSENS is stopped. |
| 1 | The APBA clock for the TSENS is enabled. |
Bit 11 – FREQM FREQM APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the FREQM is stopped. |
| 1 | The APBA clock for the FREQM is enabled. |
Bit 10 – EIC EIC APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the EIC is stopped. |
| 1 | The APBA clock for the EIC is enabled. |
Bit 9 – RTC RTC APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the RTC is stopped. |
| 1 | The APBA clock for the RTC is enabled. |
Bit 8 – WDT WDT APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the WDT is stopped. |
| 1 | The APBA clock for the WDT is enabled. |
Bit 7 – GCLK GCLK APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the GCLK is stopped. |
| 1 | The APBA clock for the GCLK is enabled. |
Bit 6 – SUPC SUPC APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the SUPC is stopped. |
| 1 | The APBA clock for the SUPC is enabled. |
Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the OSC32KCTRL is stopped. |
| 1 | The APBA clock for the OSC32KCTRL is enabled. |
Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the OSCCTRL is stopped. |
| 1 | The APBA clock for the OSCCTRL is enabled. |
Bit 3 – RSTC RSTC APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the RSTC is stopped. |
| 1 | The APBA clock for the RSTC is enabled. |
Bit 2 – MCLK MCLK APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the MCLK is stopped. |
| 1 | The APBA clock for the MCLK is enabled. |
Bit 1 – PM PM APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the PM is stopped. |
| 1 | The APBA clock for the PM is enabled. |
Bit 0 – PAC PAC APBA Clock Enable
| Value | Description |
|---|---|
| 0 | The APBA clock for the PAC is stopped. |
| 1 | The APBA clock for the PAC is enabled. |