17.8.6 AHB Mask

Name: AHBMASK
Offset: 0x10
Reset: 0x000003CFF
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   APBDDIVAS PACCAN1CAN0 
Access R/WR/WR/WR/WR/W 
Reset 11100 
Bit 76543210 
 DMACHSRAMNVMCTRLHMATRIXHSDSUAPBCAPBBAPBA 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bit 13 – APBD APBD AHB Clock Enable. This bit field is only available for SAMC2x "N" series devices.

ValueDescription
0 The AHB clock for the APBD is stopped.
1 The AHB clock for the APBD is enabled.

Bit 12 – DIVAS DIVAS AHB Clock Enable

ValueDescription
0 The AHB clock for the DIVAS is stopped.
1 The AHB clock for the DIVAS is enabled.

Bit 10 – PAC PAC AHB Clock Enable

ValueDescription
0 The AHB clock for the PAC is stopped.
1 The AHB clock for the PAC is enabled.

Bit 9 – CAN1 CAN1 AHB Clock Enable

ValueDescription
0 The AHB clock for the CAN1 is stopped.
1 The AHB clock for the CAN1 is enabled.

Bit 8 – CAN0 CAN0 AHB Clock Enable

ValueDescription
0 The AHB clock for the CAN0 is stopped.
1 The AHB clock for the CAN0 is enabled.

Bit 7 – DMAC DMAC AHB Clock Enable

ValueDescription
0 The AHB clock for the DMAC is stopped.
1 The AHB clock for the DMAC is enabled.

Bit 6 – HSRAM HSRAM AHB Clock Enable

ValueDescription
0 The AHB clock for the HSRAM is stopped.
1 The AHB clock for the HSRAM is enabled.

Bit 5 – NVMCTRL NVMCTRL AHB Clock Enable

ValueDescription
0 The AHB clock for the NVMCTRL is stopped.
1 The AHB clock for the NVMCTRL is enabled.

Bit 4 – HMATRIXHS HMATRIXHS AHB Clock Enable

ValueDescription
0 The AHB clock for the HMATRIXHS is stopped.
1 The AHB clock for the HMATRIXHS is enabled.

Bit 3 – DSU DSU AHB Clock Enable

ValueDescription
0 The AHB clock for the DSU is stopped.
1 The AHB clock for the DSU is enabled.

Bit 2 – APBC APBC AHB Clock Enable

ValueDescription
0 The AHB clock for the APBC is stopped.
1 The AHB clock for the APBC is enabled

Bit 1 – APBB APBB AHB Clock Enable

ValueDescription
0 The AHB clock for the APBB is stopped.
1 The AHB clock for the APBB is enabled.

Bit 0 – APBA APBA AHB Clock Enable

ValueDescription
0 The AHB clock for the APBA is stopped.
1 The AHB clock for the APBA is enabled.