22.4.2.5.1 Waveform Output Operations

The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled:
  1. Choose a waveform generation mode using the Waveform Generation Mode bit field in the Waveform Generation Control register (WAVE.WAVEGEN).
  2. Optionally invert the waveform output WO[n] by setting the corresponding Waveform Output n Invert Enable bit in the Driver Control register (DRVCTRL.INVENn).
  3. Configure the pins as output using the I/O Pin Controller. Refer to the I/O Pin Controller (PORT) section for details.

The counter value is continuously compared with each CC[n] value. On a comparison match, the Match or Capture Channel n bit in the Interrupt Flag Status and Clear register (INTFLAG.MCn) will be set (see Normal Frequency Operation). An interrupt and/or event can be generated on comparison match if enabled. The same condition also generates a DMA request.

There are four waveform configurations for the Waveform Generation Operation bit group in the Waveform register (WAVE.WAVEGEN). These configurations influence how the waveform is generated and impose restrictions on the TOP value. The available configurations are:
  • Normal frequency (NFRQ)
  • Match frequency (MFRQ)
  • Normal pulse-width modulation (NPWM)
  • Match pulse-width modulation (MPWM)

When using NPWM or NFRQ configuration, the TOP value is determined by the counter resolution. In 8-bit Counter mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16- and 32-bit Counter mode, TOP is fixed to the maximum (MAX) value of the counter.

The table below shows the update counter and overflow event/interrupt generation conditions in different operation modes.

Table 22-3. Counter Update and Overflow Event/interrupt Conditions in TC
NameOperationTOPUpdateOutput Waveform OVF Interrupt/Event
On MatchOn UpdateUpDown
NFRQNormal FrequencyPERTOP/ ZEROToggleStableTOPZERO
MFRQMatch FrequencyCC[0]TOP/ ZEROToggleStableTOPZERO
NPWMNormal PWMPERTOP/ ZEROSee description belowTOPZERO
MPWMMatch PWMCC[0]TOP/ ZEROSee description belowTOPZERO
Normal Frequency Generation (NFRQ)

For Normal Frequency Generation, the period time (T) is controlled by the TOP value. The waveform output (WO[n]) is toggled on each compare match between COUNT and CC[n], and the corresponding Match or Capture Channel n Interrupt Flag (INTFLAG.MCn) will be set.

Figure 22-4. Normal Frequency Operation
Match Frequency Generation (MFRQ)

For Match Frequency Generation, the period time (T) is controlled by the CC[0] register instead of TOP. WO[0] toggles on each update condition.

Figure 22-5. Match Frequency Operation
Normal Pulse-Width Modulation Operation (NPWM)

NPWM uses single-slope PWM generation.

For single-slope PWM generation, the period time (T) is controlled by the TOP value, and the CC[n] controls the duty cycle of the generated waveform output. When counting upwards, WO[n] is set at the start or on compare match between the COUNT and TOP values, and cleared on a compare match between COUNT and CC[n] register values. When counting downwards, the WO[n] is cleared at the start or on a compare match between the COUNT and ZERO values, and set on compare match between COUNT and the CC[n] register value.

The following equation calculates the exact resolution in bits for a single-slope PWM (RPWM_SS) waveform:


RPWM_SS=log(TOP+1)log(2)

The PWM frequency (fPWM_SS) depends on the TOP value and the peripheral clock frequency (fGCLK_TC), and can be calculated by the following equation:

fPWM_SS=fGCLK_TCN(TOP+1)

Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).

Match Pulse-Width Modulation Operation (MPWM)

In MPWM mode, the output of WO[1] depends on CC1 as shown in the figure below. On every overflow or underflow, a one-TC-clock-cycle negative pulse is output on WO[0] (not shown in the figure).

Figure 22-6. Match PWM Operation