23.4.3.7 Waveform Extension

The “Waveform Extension Stage Details” figure below shows a schematic diagram of the actions of the two optional units that follow the recoverable fault stage on a port pin pair: Output Matrix (OTMX) and Pattern Generation.

The output matrix (OTMX) unit distributes Compare Channels (CCn), according to the selectable configurations shown in the table below.

The following comments provide an explanation for each of the four Output Matrix Chanel Pin Routing Configurations. The configuration can be written to the Output Matrix bit field in the Waveform Extension Control register (WEXCTRL.OTMX).

• Configuration 0x0 is the default configuration. The channel location is the default, and channels are distributed to outputs modulo the number of channels. Channel 0 is routed to the Output matrix output OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1], and so on.
• Configuration 0x1 distributes the channels to outputs modulo half the number of channels. This assigns twice as many output locations to the lower channels compared to the default configuration. This can be used, for example, to control the four transistors of a full bridge using only two compare channels.

  With pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible drive of a full bridge in all quadrant configurations.

• Configuration 0x2 distributes Compare Channel 0 (CC0) to all port pins. With pattern generation, this configuration can be used to control a stepper motor.
• Configuration 0x3 distributes the Compare Channel 0 (CC0) to the first output, and the Compare Channel 1 (CC1) to all other outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED strings with a boost stage.

The pattern generator unit produces a synchronized bit pattern across the port pins to which it is connected. The pattern generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC), stepper motors, and full bridge control. See also the “Pattern Generator Block Diagram” figure below.

As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition set by the timer/counter waveform generation operation. If synchronization is not required by the application, the software can simply access the bits directly in the Pattern Generation Output Enable and Pattern Generation Output Value fields in the Pattern register (PATT.PGE and PATT.PGV).