23.4.3.3 Ramp Operations
Three ramp operation modes are supported. All of them require the timer/counter to be running in single-slope PWM generation. The ramp mode is selected by writing to the Ramp Operation bit field in the Waveform register (WAVE.RAMP).
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated to power factor correction (PFC), half-bridge and push-pull SMPS topologies, where two consecutive timer/counter cycles are interleaved. In cycle A, the odd channel output is disabled, and in cycle B, the even channel output is disabled. The ramp index changes after each update, but it can be modified by software using the Ramp Index Command bit field in the Control B Set register (CTRLBSET.IDXCMD). All RAMP2 operations suport only up-counting mode (when the Counter Direction bit in the Control B Clear register (CTRLBCLR.DIR) is cleared).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled by the Period register (PER). The PER value can be different on each ramp if the Circular Period Enable bit in the Waveform register (WAVE.CIPEREN) is set. This mode uses a two-channel TCC to generate two output signals.
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2, but the Compare/Capture Value in the Compare/Capture Channel 0 register (CC0.CC) controls both WO[0] and WO[1] waveforms when the corresponding circular buffer option is enabled (WAVE.CIPEREN is set). The waveform polarity is the same on both outputs. Channel 1 can be used in capture mode.
Critical RAMP2 (RAMP2C) Operation
Critical RAMP2 operation provides a way to meet RAMP2 operation requirements without the update constraint associated with the use of circular buffers. In this mode, CC0.CC controls the period of ramp A, and PER.PER controls the period of ramp B. When using more than two channels, the WO[0] output is controlled by CC2.CC (HIGH) and CC0.CC (LOW). With two channels, a pulse on WO[0] will last the entire period of ramp A if the Channel Polarity 0 bit in the Waveform register (WAVE.POL0) is cleared.
