31.7.5 Interrupt Enable Set

This register allows the user to enable an interrupt without performing a read-modify-write operation. Changes to this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).

Name:	INTENSET
Offset:	0x16
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
	ERROR						SB	MB
Access	R/W						R/W	R/W
Reset	0						0	0

Bit 7 – ERROR Error Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

Value	Description
0	Error interrupt is disabled
1	Error interrupt is enabled

Bit 1 – SB Client on Bus Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.

Value	Description
0	The Client on Bus interrupt is disabled
1	The Client on Bus interrupt is enabled

Bit 0 – MB Host on Bus Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.

Value	Description
0	The Host on Bus interrupt is disabled
1	The Host on Bus interrupt is enabled