31.7.2 Control B
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ACKACT | CMD[1:0] | ||||||||
| Access | R/W | W | W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QCEN | SMEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 18 – ACKACT Acknowledge Action
This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
| Value | Description |
|---|---|
| 0 | Send ACK |
| 1 | Send NACK |
Bits 17:16 – CMD[1:0] Command
Writing to these bits triggers a host operation as described below. The CMD bits are strobe bits and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated start or stop condition. The CTRLB.ACKACT bit and the CMD bits can be written simultaneously, in which case the acknowledge action will be updated before the command is triggered.
Commands can only be issued when either the Client on Bus interrupt flag
(INTFLAG.SB) or the Host on Bus interrupt flag
(INTFLAG.MB) is ‘1’.
If CMD 0x1 is issued, a repeated start will be generated,
followed by the transmission of the current
address in ADDR.ADDR. If another address is
desired, ADDR.ADDR must be written instead of the
CMD bits. This will trigger a repeated start
followed by the transmission of the new
address.
Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).
| CMD[1:0] | Direction | Action |
|---|---|---|
| 0x0 | X | (No action) |
| 0x1 | X | Execute acknowledge action succeeded by repeated Start |
| 0x2 | 0 (Write) | No operation |
| 1 (Read) | Execute acknowledge action, followed by a byte read operation | |
| 0x3 | X | Execute acknowledge action, followed by issuing a stop condition |
Bit 9 – QCEN Quick Command Enable
| Value | Description |
|---|---|
| 0 | Quick Command is disabled |
| 1 | Quick Command is enabled |
Bit 8 – SMEN Smart Mode Enable
When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
| Value | Description |
|---|---|
| 0 | Smart mode is disabled |
| 1 | Smart mode is enabled |