31.7.1 Control A

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized


Bit	31	30	29	28	27	26	25	24
		LOWTOUTEN	INACTOUT[1:0]		SCLSM		SPEED[1:0]
Access		R/W	R/W	R/W	R/W		R/W	R/W
Reset		0	0	0	0		0	0


Bit	23	22	21	20	19	18	17	16
	SEXTTOEN	MEXTTOEN	SDAHOLD[1:0]					PINOUT
Access	R/W	R/W	R/W	R/W				R/W
Reset	0	0	0	0				0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RUNSTDBY			MODE[2:0]			ENABLE	SWRST
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0

Bit 30 – LOWTOUTEN SCL Low Time-Out

This bit enables the SCL low time-out. If SCL is held low for 25–35 ms, the host will release its clock hold, if enabled, and complete the current transaction. A stop condition will automatically be transmitted.

INTFLAG.SB or INTFLAG.MB will be set as normal, but the clock hold will be released. The STATUS.LOWTOUT and STATUS.BUSERR status bits will be set.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Time-out is disabled
1	Time-out is enabled

Bits 29:28 – INACTOUT[1:0] Inactive Time-Out

If the inactive bus time-out is enabled and the bus is inactive for longer than the time-out setting, the bus state logic will be set to IDLE. An inactive bus arises when either an I²C host or client is holding the SCL low.

Enabling this option is necessary for SMBus compatibility, but it can also be used in a non-SMBus set-up.

Calculated time-out periods are based on a 100 kHz bus clock.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0x0	DIS	Disabled
0x1	55US	5-6 SCL cycle time-out (50-60 µs)
0x2	105US	10-11 SCL cycle time-out (100-110 µs)
0x3	205US	20-21 SCL cycle time-out (200-210 µs)

Bit 27 – SCLSM SCL Clock Stretch Mode

This bit controls when SCL will be stretched for software interaction.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	SCL stretch according to Figure 31-5
1	SCL stretch only after ACK bit, Figure 31-6

Bits 25:24 – SPEED[1:0] Transfer Speed

These bits define bus speed.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	SM_MODE	Standard-mode (Sm) and Fast-mode (Fm)
0x1	FASTPLUS_MODE	Fast-mode Plus (Fm+)
Other	—	Reserved

Bit 23 – SEXTTOEN Client SCL Low Extend Time-Out

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25 ms from the initial START to a STOP, the host will release its clock hold if enabled, and complete the current transaction. A STOP will be transmitted automatically.

SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will also be set.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Time-out is disabled
1	Time-out is enabled

Bit 22 – MEXTTOEN Host SCL Low Extend Time-Out

This bit enables the host SCL low extend time-out. If SCL is cumulatively held low for greater than 10 ms from START-to-ACK, ACK-to-ACK, or ACK-to-STOP the host will release its clock hold if enabled, and complete the current transaction. A STOP will be transmitted automatically.

SB or MB will be set as normal, but CLKHOLD will be released. The MEXTTOUT and BUSERR status bits will also be set.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Time-out is disabled
1	Time-out is enabled

Bits 21:20 – SDAHOLD[1:0] SDA Hold Time

These bits define the SDA hold time with respect to the negative edge of SCL.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	DIS	SDA hold time is disabled
0x1	75NS	SDA hold time is 50–100 ns
0x2	450NS	SDA hold time is 300–600 ns
0x3	600NS	SDA hold time is 400–800 ns

Bit 16 – PINOUT Pin Usage

This bit sets the pin usage to either two- or four-wire operation:

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	4-wire operation is disabled
1	4-wire operation is enabled

Bit 7 – RUNSTDBY Run in Standby

This bit defines the functionality in Standby Sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	GCLK_SERCOMx_CORE is disabled and the I²C host will not operate in Standby sleep mode
1	GCLK_SERCOMx_CORE is enabled in all sleep modes

Bits 4:2 – MODE[2:0] Operating Mode

This bit field controls the SERCOM mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	USART_EXT	USART with external clock
0x1	USART_INT	USART with internal clock
0x2	SPI_SLAVE	SPI Client mode
0x3	SPI_MASTER	SPI Host mode
0x4	I2C_SLAVE	I²C Client mode
0x5	I2C_MASTER	I²C Host mode

Bit 1 – ENABLE Enable

Note:

This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
This bit is not enable-protected.

Value	Description
0	The peripheral is disabled or being disabled
1	The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state and disables the SERCOM.

Writing ‘1’ to CTRLA.SWRST always takes precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register during the reset will return the reset value of the register.

Note:

This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST synchronization is complete.
This bit is not enable-protected.

Value	Description
0	There is no reset operation in progress
1	The reset operation is in progress