24.5.3 Clocks

The EVSYS bus clock (CLK_EVSYS_APB) can be enabled and disabled in the Main Clock (MCLK), and its default state can be found in the Peripheral Clock Masking section of the MCLK – Main Clock chapter.

Each EVSYS channel has a dedicated generic clock (GCLK_EVSYS_CHn), which is used for event detection and propagation for each channel. These clocks must be configured and enabled in the generic clock controller before using the EVSYS. Refer to the GCLK – Generic Clock Controller chapter for details.