24.5.5 Interrupts
The interrupt request line, also known as the interrupt vector, is connected to the interrupt controller. To use EVSYS interrupts, the interrupt controller must be configured in advance, including enabling the interrupt line globally. For further information, refer to the NVIC – Nested Vectored Interrupt Controller section.
Each interrupt source has an interrupt flag
which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when
the interrupt condition occurs. Each interrupt can be individually enabled by writing a
‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a ‘1’ to the corresponding bit in the
Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt source is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EVSYS is reset. Refer to the INTFLAG register description for details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate a single combined interrupt request to the NVIC. Therefore, the INTFLAG register must be read to determine what the interrupt condition is.
| Vector Name | Source Name | Condition | Dependency |
|---|---|---|---|
| EVSYS | OVRn | An event occurs before the previous event on channel n has been handled by all event users, or when any of the event users are not ready. Refer to Overrun Channel Detection for further information. | The channel path synchronizer is configured to be either synchronous or resynchronized in the Path Selection bit field in Channel n Control register (CHANNEL[n].PATH is 0x0 or 0x1) |
| EVDn | An event from the event generator configured for channel n is detected. Refer to Channel Event Detection for further information. |