24.6 Register Summary


Offset	Name	Bit Pos.	7	6	4	3	2	1	0
0x00	CTRLA	7:0							SWRST
0x01 ... 0x0B	Reserved
0x0C	CHSTATUS	7:0				USRRDY3	USRRDY2	USRRDY1	USRRDY0
		15:8
		23:16				CHBUSY3	CHBUSY2	CHBUSY1	CHBUSY0
		31:24
0x10	INTENCLR	7:0				OVR3	OVR2	OVR1	OVR0
		15:8
		23:16				EVD3	EVD2	EVD1	EVD0
		31:24
0x14	INTENSET	7:0				OVR3	OVR2	OVR1	OVR0
		15:8
		23:16				EVD3	EVD2	EVD1	EVD0
		31:24
0x18	INTFLAG	7:0				OVR3	OVR2	OVR1	OVR0
		15:8
		23:16				EVD3	EVD2	EVD1	EVD0
		31:24
0x1C	SWEVT	7:0				CHANNEL3	CHANNEL2	CHANNEL1	CHANNEL0
		15:8
		23:16
		31:24
0x20	CHANNEL[0]	7:0		EVGEN[6:0]
		15:8	ONDEMAND	RUNSTDBY		EDGSEL[1:0]		PATH[1:0]
		23:16
		31:24
0x24	CHANNEL[1]	7:0		EVGEN[6:0]
		15:8	ONDEMAND	RUNSTDBY		EDGSEL[1:0]		PATH[1:0]
		23:16
		31:24
0x28	CHANNEL[2]	7:0		EVGEN[6:0]
		15:8	ONDEMAND	RUNSTDBY		EDGSEL[1:0]		PATH[1:0]
		23:16
		31:24
0x2C	CHANNEL[3]	7:0		EVGEN[6:0]
		15:8	ONDEMAND	RUNSTDBY		EDGSEL[1:0]		PATH[1:0]
		23:16
		31:24
0x30 ... 0x7F	Reserved
0x80	USER[0]	7:0			CHANNEL[4:0]
		15:8
		23:16
		31:24
...
0xD4	USER[21]	7:0			CHANNEL[4:0]
		15:8
		23:16
		31:24