30.6.1 Control A

Name:	CTRLA
Offset:	0x00
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized


Bit	31	30	29	28	27	26	25	24
		DORD	CPOL	CPHA	FORM[3:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			DIPO[1:0]				DOPO[1:0]
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0


Bit	15	14	13	12	11	10	9	8
								IBON
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
	RUNSTDBY			MODE[2:0]			ENABLE	SWRST
Access	R/W			R/W	R/W	R/W	R/W	R/W
Reset	0			0	0	0	0	0

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the shift register.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	MSB	MSb is transferred first
1	LSB	LSb is transferred first

Bit 29 – CPOL Clock Polarity

In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	IDLE_LOW	SCK is low when IDLE. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1	IDLE_HIGH	SCK is high when IDLE. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.

Bit 28 – CPHA Clock Phase

In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Name	Description
0	LEADING_EDGE	The data is sampled on a leading SCK edge and changed on a trailing SCK edge
1	TRAILING_EDGE	The data is sampled on a trailing SCK edge and changed on a leading SCK edge

Bits 27:24 – FORM[3:0] Frame Format

This bit field selects the various frame formats supported by the SPI in Client mode. When the SPI_FRAME_WITH_ADDR format is selected, the first byte received is checked against the ADDR register.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	SPI_FRAME	SPI Frame
0x2	SPI_FRAME_WITH_ADDR	SPI Frame with Address

Bits 21:20 – DIPO[1:0] Data In Pinout

These bits define the data in (DI) pad configurations.

In host operation, DI is MISO.

In client operation, DI is MOSI.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	MUX0	SERCOM PAD[0] is used as data input
0x1	MUX1	SERCOM PAD[1] is used as data input
0x2	MUX2	SERCOM PAD[2] is used as data input
0x3	MUX3	SERCOM PAD[3] is used as data input

Bits 17:16 – DOPO[1:0] Data Out Pinout

This bit defines the available pad configurations for data out (DO), the serial clock (SCK) and the SPI select (SS).

In host operation, DO is MOSI.

In client operation, DO is MISO.

Note:

This bit field is enable-protected. This bit field is not synchronized.
In host operation, the SPI select line (SS) is only controlled by DOPO when CTRLB.MSSEN is set to ’1’.

Value	Name	Description
0x0	MUX0	PAD[0]=DO, PAD[1]=SCK, PAD[2]=SS
0x1	MUX1	PAD[2]=DO, PAD[3]=SCK, PAD[1]=SS
0x2	MUX2	PAD[3]=DO, PAD[1]=SCK, PAD[2]=SS
0x3	MUX3	PAD[0]=DO, PAD[3]=SCK, PAD[1]=SS

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	STATUS.BUFOVF is set when it occurs in the data stream
1	STATUS.BUFOVF is set immediately upon buffer overflow

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in Standby sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	The SPI is disabled in Standby sleep mode. In Client mode, the SPI is disabled immediately when Standby sleep mode is entered. In Host mode, the SPI is disabled when the ongoing transaction is finished.
1	The SPI is enabled in Standby sleep mode

Bits 4:2 – MODE[2:0] Operating Mode

This bit field controls the SERCOM mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	USART_EXT	USART with external clock
0x1	USART_INT	USART with internal clock
0x2	SPI_SLAVE	SPI Client mode
0x3	SPI_MASTER	SPI Host mode
0x4	I2C_SLAVE	I²C Client mode
0x5	I2C_MASTER	I²C Host mode

Bit 1 – ENABLE Enable

Note:

This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
This bit is not enable-protected.

Value	Description
0	The peripheral is disabled or being disabled
1	The peripheral is enabled or being enabled

Bit 0 – SWRST Software Reset

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing ‘1’ to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Note:

This bit is write-synchronized: SYNCBUSY.SWRST must be checked to ensure the CTRLA.SWRST synchronization is complete.
This bit is not enable-protected.

Value	Description
0	There is no reset operation in progress
1	The reset operation is in progress