30.6.2 Control B

Name:	CTRLB
Offset:	0x04
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected, Write-Synchronized


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							RXEN
Access							R/W
Reset							0


Bit	15	14	13	12	11	10	9	8
	AMODE[1:0]		MSSEN				SSDE
Access	R/W	R/W	R/W				R/W
Reset	0	0	0				0


Bit	7	6	5	4	3	2	1	0
		PLOADEN				CHSIZE[2:0]
Access		R/W				R/W	R/W	R/W
Reset		0				0	0	0

Bit 17 – RXEN Receiver Enable

Writing ‘0’ to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared.

Writing ‘1’ to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as ‘1’.

This bit is not enable-protected.

Value	Description
0	The receiver is disabled or being enabled
1	The receiver is enabled or it will be enabled when SPI is enabled

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the Client addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode.

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0x0	MASK	ADDRMASK is used as a mask to the ADDR register
0x1	2ADDRS	The client responds to the two unique addresses in ADDR and ADDRMASK
0x2	RANGE	The client responds to the range of addresses between and including ADDR and ADDRMASK with ADDR as the upper limit

Bit 13 – MSSEN Host SPI Select Enable

This bit enables hardware SPI select (SS) control. When Hardware SPI Select Control is enabled (CTRLB.MSSEN), the SS pin goes low before, and high after each transferred word. Refer to the Hardware Controlled SS section for details.

Note:

This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Hardware SS control is disabled
1	Hardware SS control is enabled

Bit 9 – SSDE SPI Select Low Detect Enable

This bit enables wake up when the SPI select (SS) pin transitions from high to low.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	SS low detector is disabled
1	SS low detector is enabled

Bit 6 – PLOADEN Client Data Preload Enable

Setting this bit will enable preloading of the client shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the shift register.

The Preload function must not be used if the Host cannot maintain the SS low until transmission is complete.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Preloading of Client shift register when no transfer in progress is disabled
1	Preloading of Client shift register when no transfer in progress is enabled

Bits 2:0 – CHSIZE[2:0] Character Size

Note: This bit field is enable-protected. This bit field is not synchronized.

Value	Name	Description
0	8_BIT	Eight bits
1	9_BIT	Nine bits
Other	—	Reserved