25.4.5 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

• Software Reset (SWRST) bit in the Control A (CTRLA) register
• Enable (ENABLE) bit in the Control A (CTRLA) register

Required write-synchronization is denoted by the “Write-Synchronized” property in the register description.