30.4.2.5.1 Host

In Host mode, when Host SPI Select Enable (CTRLB.MSSEN) is ’1’, hardware controls the SS line.

When Host SPI Select Enable (CTRLB.MSSEN) is ‘0’, the SS line must be configured as an output. Any general purpose I/O pin can be used as SS. When the SPI is ready for a data transaction, software must pull the SS line low.

When writing a character to the Data register (DATA), the character will be transferred to the shift register. Once the content of TxDATA has been transferred to the shift register, the Data Register Empty flag in the Interrupt Flag Status and Clear register (INTFLAG.DRE) will be set, and a new character can be written to DATA.

Each time a character is shifted out from the host, another character is simultaneously shifted in from the client. If the receiver is enabled (CTRLA.RXEN=1), the contents of the shift register are transferred to the two-level receive buffer. The transfer occurs in the same clock cycle as the last data bit is shifted in. Then, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) is set. The received data can be retrieved by reading DATA register.

When the last character has been transmitted and there is no valid data in the DATA register, the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set. When the transaction is finished, the host must pull the SS line high to notify the client. If Host SPI Select Enable (CTRLB.MSSEN) is set to ‘0’, the software must pull the SS line high.