30.4.2.5.2 Client

In Client mode, the SPI interface will remain inactive with the MISO line tri-stated as long as the SS pin is held high. Software may update the contents of the DATA register at any time, as long as the Data Register Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.

When SS is pulled low and SCK is running, the client will sample and shift out data according to the configured transaction mode. Once the contents of TxDATA have been loaded into the shift register, INTFLAG.DRE will be set, and new data can be written to the DATA register.

Similar to the host, the client will receive one character for each character transmitted. A character is transferred into the two-level receive buffer in the same clock cycle that its last data bit is received. The received character can be retrieved from the DATA register when the Receive Complete interrupt flag (INTFLAG.RXC) is set.

When the host pulls the SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) will be set.

After DATA is written, it takes up to three SCK clock cycles for the content of the DATA register is ready to load into the shift register at the next character boundary. As a result, the first character transferred in an SPI transaction will not be the content of the DATA register. This can be avoided by using the preloading feature. Refer to Preloading of the Client Shift Register for more information.

When transmitting several characters in one SPI transaction, data must be written to the DATA register with at least three SCK clock cycles remaining in the current character transmission. If this criteria is not met, the previously received character will be transmitted.

Once the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.