12.6.1 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation.
Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSCHFRDY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 4 – OSCHFRDY OSCHF Ready Interrupt Enable
Writing a ‘0’ to this bit has no
effect.
Writing a ‘1’ to this bit clears the OSCHF
Ready Interrupt Enable bit, thereby disabling the OSCHF is Ready interrupt.
| Value | Description |
|---|---|
| 0 | The OSCHF Ready interrupt is disabled |
| 1 | The OSCHF Ready interrupt is enabled |