6.5.8.4.2 Exit Debug Mode

The processor exits the Debug state:

  • When the debugger writes ‘0’ to DHCSR.C_HALT
  • Upon receipt of an external restart request

If software clears DHCSR.C_HALT to ‘0’ while the processor is in Debug state, a subsequent read of the DHCSR that returns ‘1’ for both C_HALT and S_HALT indicates that the processor has re-entered the Debug state because it has detected a new debug event.

Reference: ARM DDI 0403E.b, C1.5.4 Exiting Debug state

Table 6-28. Exit Debug Mode Sequence
Stepsrddi_dap
Exit Debug modeWriteD32(DHCSR, (DBGKEY | C_HALT))