19.5.5 Interrupts

The interrupt request line, also known as the interrupt vector, is connected to the interrupt controller. To use DMAC interrupts, the interrupt controller must be configured in advance, including enabling the interrupt line globally. For further information, refer to the NVIC - Nested Vectored Interrupt Controller section.

Each interrupt source has an interrupt flag which is in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register. The flag is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a ‘1’ to the corresponding bit in the Channel Interrupt Enable Set (CHINTENSET) register, and disabled by writing a ‘1’ to the corresponding bit in the Channel Interrupt Enable Clear (CHINTENCLR) register.

CHINTFLAG, CHINTENSET and CHINTENCLR reflects the interrupt status and configuration of the channel currently selected in the Channel ID (CHID) register. The Interrupt Status (INTSTATUS) register or Interrupt Pending (INTPEND) register must be used to determine which value should be written to CHID to handle a set interrupt flag. INTSTATUS indicates all channels with a pending interrupt, while INTPEND will indicate the ID and interrupt flag status of the lowest-numbered DMA channel that has a pending interrupt.

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt source is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the peripheral is reset. Refer to the CHINTFLAG register description for details on how to clear interrupt flags.

All interrupt requests from the peripheral are ORed together on system level to generate a single combined interrupt request to the NVIC. Therefore, the CHINTFLAG register must be read to determine what the interrupt condition is.