18.4.2.3 Programming

The programming procedure for the Flash and SRAM memories is as follows:

1. At power-up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (refer to Power-On Reset (POR) characteristics). The system remains in this static state until the internally regulated supplies have reached a safe operating level.
2. The Power Manager (PM) starts, and the clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external Reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger cold-plugging procedure.
4. The debugger generates a clock signal on the SWCLK pin, and the Debug Access Port (DAP) receives a clock.
5. The CPU remains in Reset due to the cold-plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased before programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET or toggling power. Ensure that the SWCLK pin is high when releasing RESET to prevent extending the CPU reset.