3 Design Description

The following figure shows a high-level block diagram of the design.

The video input is received through an HDMI compliant video source through the HDMI RX port. The serial HDMI data is converted to parallel data by Transceiver (XCVR). XCVR is configured for four lanes for HDMI video reception and transmission. The XCVR Lane 3 is a clock lane and remaining three lanes 0, 1 and 2 are used as data channels. XCVR is configured for 1485 Mbps with 40 bits parallel data width to serialize four pixels per clock.

The 40 bits (4 pixels) data received at HDMI RX IP is decoded as either a video data or an auxiliary data, and the respective valid signals and frame control signals are generated. The decoded video data and audio data are packed and written into a FIFO. The FIFO output data is unpacked to video and audio data, which are given as inputs to the HDMI TX IP. The HDMI TX IP encodes the data using TMDS encoding. The encoded data is serialized by XCVR and sent to HDMI TX port. The display connected to the HDMI TX port receives the encoded data from the HDMI TX IP, which is the same video and audio as the HDMI RX input.