3.3 Clocking Structure

The design uses the following clocks:

  • The 27 MHz fabric clock is given to CLOCK_INIT, which then provides a 27 MHz clock to PF_CCC_C0. This component generates a 50 MHz clock, used as the AXI4-Lite clock, for both HDMI_RX and HDMI_TX for AXI configuration.
  • The 148.5 MHz oscillator provides a reference clock to XCVR_REF_CLK which gives a 148.5 MHz clock to PF_CCC_C2. This setup generates an Extended Display Identification Data (EDID) clock of 150 MHz, which is REF_150M_CLK for HDMI_RX, as shown in the following figure.

The following figure shows the clocking structure of the design.

Figure 3-7. Clocking Structure