3.1 Hardware Implementation
(Ask a Question)The following figures show the Libero SoC implementation of the top-level SmartDesign.
The top-level HDMI loopback design includes the following key IP cores:
- XCVR
- HDMI TX IP
- HDMI RX IP
- FIFO
- PROC SUBSYSTEM
XCVR is configured in Full-Duplex mode, as the system receives Transition Minimized Differential Signaling (TMDS) data and transmits the encoded TMDS. The XCVR uses LANE 3 for clock data, LANE_0_JA_CLK as the clock source for PF_TX_PLL. The HDMI_RX input clocks for the Blue (B), Green (G), and Red (R) channels are driven by LANE_0_RX_CLK, LANE_1_RX_CLK, and LANE_2_RX_CLK, respectively. Correspondingly, the HDMI_TX input clocks for the B, G, and R channels are provided by LANE_0_TX_CLK_R, LANE_1_TX_CLK_R, and LANE_2_TX_CLK_R, respectively. LANE_0, LANE_1, and LANE_2 serve as the data lanes carrying the Blue, Green, and Red channel data of HDMI_RX, respectively. In this system, the XCVR data rate is selected to support Full High Definition (FHD) video data transmission and reception at 60 FPS. XCVR serializes or deserializes the HDMI 40 bits data that contains four pixels where MSB 10 bits represent the latest pixel.
The HDMI RX IP is configured with four pixels per clock for native interface. The following figure shows the HDMI RX IP configurator.
The HDMI RX IP decodes the TMDS data to video and audio data. The HDMI RX IP can be configured to operate in one pixel per clock or four with the interface type as Native and AXI4.
The FIFO core passes the decoded data of video and audio signals to HDMI TX IP for encoding. The HDMI TX IP is configured in Audio Mode as Enable to encode the audio data along with the video data.
