3.2 I/O Ports
(Ask a Question)The following table lists the important I/O ports of the design.
I/O Port | Direction | Description |
---|---|---|
LANE0_RXD_N | Input | Lane 0 RX channel N |
LANE0_RXD_P | Input | Lane 0 RX channel P |
LANE1_RXD_N | Input | Lane 1 RX channel N |
LANE1_RXD_P | Input | Lane 1 RX channel P |
LANE2_RXD_N | Input | Lane 2 RX channel N |
LANE2_RXD_P | Input | Lane 2 RX channel P |
LANE3_RXD_N | Input | Lane 3 RX channel N |
LANE3_RXD_P | Input | Lane 3 RX channel P |
REF_CLK_PAD_N | Input | Reference clock N |
REF_CLK_PAD_P | Input | Reference clock P |
REF_CLK_27_MHz | Input | Reference clock |
REF_CLK_PAD_N_CABLE_CLK | Input | Reference clock cable clock N |
REF_CLK_PAD_P_CABLE_CLK | Input | Reference clock cable clock P |
SDA_RX_O | Output | Serial data |
SCL_RX_I | Input | Serial clock |
HPD_TX_I | Input | Hot plug detect input for TX |
HPD_RX_5V_N | Input | Hot plug detect input for RX |
HDMI_TX_SDA | Output | Serial data |
HDMI_TX_SCL | Output | Serial clock |
LANE0_TXD_N | Output | Lane 0 TX channel N |
LANE0_TXD_P | Output | Lane 0 TX channel P |
LANE1_TXD_N | Output | Lane 1 TX channel N |
LANE1_TXD_P | Output | Lane 1 TX channel P |
LANE2_TXD_N | Output | Lane 2 TX channel N |
LANE2_TXD_P | Output | Lane 2 TX channel P |
LANE3_TXD_N | Output | Lane 3 TX channel N |
LANE3_TXD_P | Output | Lane 3 TX channel P |
HDMI_RX_HPD_N_O | Output | Hot plug detect output |