31.5.5 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGOVR | SAMPOVR | RESOVR | WCMP | SAMPRDY | RESRDY | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – TRIGOVR Trigger Overrun Interrupt Enable
This bit controls whether the interrupt for a trigger overrun is enabled or not.
| Value | Description |
|---|---|
| 0 | The Trigger Overrun interrupt is disabled |
| 1 | The Trigger Overrun interrupt is enabled |
Bit 4 – SAMPOVR Sample Overwrite Interrupt Enable
This bit controls whether the interrupt for a sample overwrite is enabled or not.
| Value | Description |
|---|---|
| 0 | The Sample Overwrite interrupt is disabled |
| 1 | The Sample Overwrite interrupt is enabled |
Bit 3 – RESOVR Result Overwrite Interrupt Enable
This bit controls whether the interrupt for a result overwrite is enabled or not.
| Value | Description |
|---|---|
| 0 | The Result Overwrite interrupt is disabled |
| 1 | The Result Overwrite interrupt is enabled |
Bit 2 – WCMP Window Comparator Interrupt Enable
This bit controls whether the interrupt for the Window Comparator is enabled or not.
| Value | Description |
|---|---|
| 0 | The Window Comparator interrupt is disabled |
| 1 | The Window Comparator interrupt is enabled |
Bit 1 – SAMPRDY Sample Ready Interrupt Enable
This bit controls whether the Sample Ready interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The Sample Ready interrupt is disabled |
| 1 | The Sample Ready interrupt is enabled |
Bit 0 – RESRDY Result Ready Interrupt Enable
This bit controls whether the Result Ready interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The Result Ready interrupt is disabled |
| 1 | The Result Ready interrupt is enabled |