31.5.9 Control E
| Name: | CTRLE |
| Offset: | 0x08 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMPDUR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – SAMPDUR[7:0] Sample Duration
This bit field controls the input sample duration in ADC clock (CLK_ADC) cycles. The sample duration without the PGA is (SAMPDUR + ½) CLK_ADC cycles.
If using the PGA, the input sample duration is (SAMPDUR + 1) CLK_ADC cycles, while the ADC PGA Sample Duration (ADCPGASAMPDUR) controls how long the ADC will sample the PGA.
If using an internal reference without PGA, SAMPDUR must be set to a value ≥ 4 µs * fCLK_ADC.