31.5.11 Command

Name: COMMAND
Offset: 0x0A
Reset: 0x00
Property: -

Bit 76543210 
 DIFFMODE[2:0] START[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – DIFF Differential

This bit controls whether the ADC conversion is Single-Ended or Differential.
ValueDescription
0x0Unsigned Single-Ended conversion. Only the ADCn.MUXPOS register is used.
0x1Signed Differential conversion. Both the ADCn.MUXPOS and ADCn.MUXNEG registers are used.

Bits 6:4 – MODE[2:0] Mode

This bit field controls the conversion mode for the ADC. Switching from one of the accumulation modes to a Single mode will reset the accumulator.
ValueNameDescription
0x0SINGLE_8BITSingle conversion with 8-bit resolution
0x1SINGLE_12BITSingle conversion with 12-bit resolution
0x2SERIESSeries with accumulation, a separate trigger for every 12-bit conversion
0x3SERIES_SCALINGSeries with accumulation and scaling, a separate trigger for every 12-bit conversion
0x4BURSTBurst with accumulation. One trigger will run SAMPNUM 12-bit conversions in one sequence.
0x5BURST_SCALINGBurst with accumulation and scaling. One trigger will run SAMPNUM 12-bit conversions in one sequence.
Other-Reserved

Bits 2:0 – START[2:0] Start Conversion

This bit field starts or stops an ADC conversion or controls how an ADC conversion will start.
Note: If the ENABLE bit in ADCn.CTRLA is ‘0’ when writing the START bit field to IMMEDIATE, it will automatically be set to STOP.
ValueNameDescription
0x0STOPStop an ongoing conversion
0x1IMMEDIATEStart a conversion immediately. This will be set back to STOP when the conversion is done unless Free-Running mode is enabled.
0x2MUXPOS_WRITEStart when a write to the MUXPOS register is done
0x3MUXNEG_WRITEStart when a write to the MUXNEG register is done
0x4EVENT_TRIGGERStart when an event is received by the ADC
Other-Reserved