Table 27-7. MATRIX2 Hosts| Host No. | Host Name | Description |
|---|
| 0 | MATRIX0 | CM4-C0-S-Bus, PDC0, PDC2, ICM |
| 1 | MATRIX3 | PDC1 |
| 2 | CM4-C1 ICode Bus | – |
| 3 | CM4-C1 DCode Bus | – |
| 4 | CM4-C1 S-Bus | – |
Table 27-8. MATRIX2 Clients| Client No. | Client Name | Description |
|---|
| 0 | MATRIX0 | Provides access through MATRIX0 to:- SRAM0 (for PDC1 and CM4 C1 S bus)
- APB Bridge 0 (for CMC4 C1 S Bus only)
- APB Bridge 3 (PMC
only for CM4 C1 S bus only)
- SRAM0 (for PDC1
only)
|
| 1 | MATRIX3 | Provides access through MATRIX3 to APB Bridge 1 |
| 2 | APB Bridge 4 | – |
| 3 | SRAM1, Port 0 | – |
| 4 | SRAM1, Port 1 | – |
| 5 | SRAM1, Port 2 | – |
| 6 | SRAM1, Port 3 | – |
| 7 | SRAM2, Port 0 | – |
| 8 | SRAM2, Port 1 | – |
| 9 | SRAM2, Port 2 | – |
| 10 | SRAM2, Port 3 | – |
Note: For consistency, each SRAM port shall have the same Privilege Protection access
management configuration.
Table 27-9. MATRIX2 Host to Client
Connections| MATRIX2
Clients | MATRIX2 Hosts |
|---|
| 0 | 1 | 2 | 3 | 4 |
|---|
| MATRIX0 | MATRIX3 | CM4-C1 ICode Bus | CM4-C1 DCode Bus | CM4-C1 S-Bus |
|---|
| 0 | MATRIX2 | – | X | – | – | X |
| 1 | MATRIX3 | X | – | – | – | X |
| 2 | APB Bridge 4 | X | – | – | – | X |
| 3 | SRAM1, Port 0 | – | – | X | – | – |
| 4 | SRAM1, Port 1 | – | – | – | X | – |
| 5 | SRAM1, Port 2 | – | – | – | – | X |
| 6 | SRAM1, Port 3 | X | X | – | – | – |
| 7 | SRAM2, Port 0 | – | – | X | – | – |
| 8 | SRAM2, Port 1 | – | – | – | X | – |
| 9 | SRAM2, Port 2 | – | – | – | – | X |
| 10 | SRAM2, Port 3 | X | X | – | – | – |
Table 27-10. MATRIX3 Hosts| Host No. | Host Name | Description |
|---|
| 0 | MATRIX2 |
- CM4-C0 S-Bus to
APB Bridge 1
- CM4-C1 S-Bus to APB Bridge 1
|
| 1 | PDC1 | – |
Table 27-11. MATRIX3 Clients| Client No. | Client Name | Description |
|---|
| 0 | MATRIX2 | – |
| 1 | APB Bridge 1 | – |
Table 27-12. MATRIX3 Host to Client
Connections| MATRIX3
Clients | MATRIX3 Hosts |
|---|
| 0 | 1 |
|---|
| MATRIX2 | PDC1 |
|---|
| 0 | MATRIX2
(1) | – | X |
| 1 | APB Bridge 1 | X | X |
Note:
- Client port provides access to
SRAM0 port 2,
SRAM1 port 3 and SRAM2 port 3 for PDC1.
