27.1.1 Application Core (CM4-C0) Matrix 0 and 1 Hosts and Clients

Table 27-1. MATRIX0 Hosts
Host No.	Host Name	Description
0	CM4-C0 ICode Bus	–
1	CM4-C0 DCode Bus	–
2	CM4-C0 S-Bus	–
3	CMCC0 (ICache/ITCM)	–
4	CMCC1 (DCache/DTCM)	–
5	MATRIX2	CM4-C1 S-Bus, PDC1
6	MATRIX1	PDC0, PDC2 and ICM

Table 27-2. MATRIX0 Clients
Client No.	Client Name	Description
0	SRAM0, Port 0	–
1	SRAM0, Port 1	–
2	SRAM0, Port 2	–
3	ROM	–
4	MATRIX1	Provides access to: QSPI QSPI through AESB APB peripherals accessible through Bridges 0 and 2
5	CPKCC	–
6	APB Bridge 3	–
7	MATRIX2	Provides access to: SRAM1 port 3 SRAM2 port 3 APB peripherals accessible through Bridges 1 and 4 of the metrology sub-system
8	CMCC0 (ICache/ITCM)	–
9	CMCC1 (DCache/DTCM)	–
10	Flash	–
11	MATRIX1	Provides access to: QSPI QSPI through AESB

Note: For consistency, each SRAM port shall have the same Privilege Protection access management configuration.

Table 27-3. MATRIX0 Host to Client Connections
MATRIX0 Clients		MATRIX0 Hosts
		0	1	2	3	4	5	6
		CM4-C0 ICode Bus	CM4-C0 DCode Bus	CM4-C0 S-Bus	CMCC0 (ICache/ITCM)	CMCC1 (DCache/DTCM	MATRIX2	MATRIX1
0	SRAM0, Port 0	–	–	X	–	–	–	–
1	SRAM0, Port 1	–	–	–	–	–	–	X
2	SRAM0, Port 2	–	–	–	–	–	X	–
3	ROM	X	X	–	–	–	–	–
4	MATRIX1	X	X	X	–	–	X	–
5	CPKCC	X	X	–	–	–	–	–
6	APB Bridge 3	–	–	X	–	–	X⁽⁵⁾	–
7	MATRIX2	–	–	X	–	–	–	X⁽²⁾
8	CMCC0 (ICache/ITCM)	X	X⁽³⁾	–	–	–	–	–
9	CMCC1 (DCache/DTCM)	–	X	–	–	–	–	–
10	Flash⁽⁴⁾	X	X	X⁽⁶⁾	X	X	–	X
11	MATRIX1	–	–	–	X	X	–	–

Note:

For consistency, each SRAM port shall have the same Privilege Protection access management configuration.
Through this port, PDC0, PDC2, and ICM can only access port 3 of SRAM1 and 2.
Connection needed to enable write of ITCM for CM4-C0.
Client Flash must be configured in NO_DEFAULT_MASTER.
Only CM4P1-S has access to APB Bridge 3 through HSMS2HSASB.
Used to access the Flash Controller Page Buffer (Write Operation) in a strongly ordered manner.

Table 27-4. MATRIX1 Hosts
Host No.	Host Name	Description
0	MATRIX0	CM4-C0-ICode and CM4-C0-DCode to QSPI and AESB CM4-C0-S-Bus to APB Bridges (0 and 2) CM4-C1-S-Bus to APB Bridge 0
1	MATRIX0	CMCC0 (I), CMCC1 (D) to QSPI and AESB
2	AESB	QSPI Cached or Non cached through AESB
3	ICM	Flash Non cached QSPI Non cached SRAM0 port1 SRAM1 port3 SRAM2 port3
4	PDC0	QSPI Non cached AESB Non cached - through AESB SRAM0 port1 SRAM1 port3 SRAM2 port3
5	PDC2	Flash Non cached QSPI Non cached SRAM0 port1 SRAM1 port3 SRAM2 port3

Table 27-5. MATRIX1 Clients
Client No.	Client Name	Description
0	QSPI	–
1	AESB	–
2	MATRIX0	Provides access to: SRAM0 port 1 SRAM1 port 3 for PDC0, PDC1 and ICM Flash for ICM
3	APB Bridge 0	–
4	APB Bridge 2	–

Table 27-6. MATRIX1 Host to Client Connections
MATRIX1 Clients		MATRIX1 Hosts
		0	1	2	3	4	5
		MATRIX0	MATRIX0	AESB	ICM	PDC0	PDC2
0	QSPI	X	X	X	X	X	X
1	AESB	X	X	–	–	X	–
2	MATRIX0	–	–	–	X	X	X
3	APB Bridge 0	X	–	–	–	X	–
4	APB Bridge 2	X	–	–	–	–	X

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