14.2.5 System Clock Tree
The ROM code configures the system clock tree according to the value of the GPBR[15] word:
| Name: | System Clock Tree |
| Reset: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[23:16] | |||||||||
| Access | |||||||||
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| KEY[15:8] | |||||||||
| Access | |||||||||
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| KEY[7:0] | |||||||||
| Access | |||||||||
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPU_CK[3:0] | PATCH_BYPASS | BR_57600 | MCK0DIV2 | MCK0DIV | |||||
| Access | |||||||||
| Reset | – | – | – | – | – | – | – | – | |
Bits 31:8 – KEY[23:0]
The ROM code ignores the value of GPBR[15] word unless the value of KEY is 0x524F4D. For any other value, the ROM code configures the system clock tree from its default settings:
- CPU_CK: 0
- MCK0DIV: 1
- MCK0DIV2: 1
- BR_57600: 0
- PATCH_BYPASS: 1
Bits 7:4 – CPU_CK[3:0] CPU Clock Frequency
| Value | Description |
|---|---|
| 0 |
CPU clock frequency is 200 MHz |
| 1 |
CPU clock frequency is 100 MHz |
| 2 | CPU clock frequency is 50 MHz |
| Others | CPU clock frequency is 200 MHz |
Bit 3 – PATCH_BYPASS Flash Patch Bypass
When the ROM code configures the system clock tree, it sets the value of the PATCH_BYPASS bit from the GPBR[15] word into the SFR_FLASH register.
Bit 2 – BR_57600 ROM Code Console Baud Rate is 57600
| Value | Description |
|---|---|
| 0 | ROM code console baud rate is 115200 |
| 1 | ROM code console baud rate is 57600 |
Bit 1 – MCK0DIV2
When the ROM code configures the system clock tree, it sets the value of the MCK0DIV2 bit from the GPBR[15] word into the PMC_CPU_CKR register.