Because the QSPI Controller interface and the QSPI Controller core use different clocks, some events must be synchronized with the core for them to take effect.
The events that require synchronization with the QSPI Controller core are:
QSPI_CR.QSPIEN
QSPI_CR.QSPIDIS
QSPI_CR.SWRST
QSPI_CR.UPDCFG
QSPI_CR.STTFR
QSPI_CR.RTOUT
QSPI_CR.LASTXFER
QSPI_RDR.RD (implies synchronization only when QSPI_MR.SMM is set to ‘1 ‘)
QSPI_TDR.TD
Before accessing any of these bits/fields, check that QSPI_SR.SYNCBSY is at ‘0’.
When the synchronization process is in progress, QSPI_SR.SYNCBSY is at ‘1’.
As long as QSPI_SR.SYNCBSY is at ‘1’, no access to the registers requiring synchronization is allowed.
When using QSPI_CR.UPDCFG to update the system configuration, it is mandatory for QSPI_SR.SYNCBSY to be at ‘0’ before and after writing QSPI_CR.UPDCFG. This ensures that the update is completed before going on to the next step.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
