35.6.3 Serial Clock Phase and Polarity
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the QSPI Serial Clock register (QSPI_SCR). The CPHA bit in the QSPI_SCR programs the clock phase. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, the interfaced client must use the same parameter values to communicate.
Only Mode 0 is supported with QSPI_MR.SMM = 1.
The table below shows the four modes and corresponding parameter settings.
| QSPI Clock Mode | QSPI_SCR.CPOL | QSPI_SCR.CPHA | Shift QSCK Edge | Capture QSCK Edge | QSCK Inactive Level |
|---|---|---|---|---|---|
| 0 | 0 | 0 | Falling | Falling | Low |
| 1 | 0 | 1 | Rising | Rising | Low |
| 2 | 1 | 0 | Rising | Rising | High |
| 3 | 1 | 1 | Falling | Falling | High |
The figures below show examples of data transfers.