35.6.4 Transfer Delays

The figure below shows several consecutive transfers while the chip select is active. Three delays can be programmed to modify the transfer waveforms:

• The delay between the deactivation and the activation of QCS, programmed by writing QSPI_MR.DLYCS. Allows to adjust the minimum time of QCS at high level.
• The delay before QSCK, programmed by writing QSPI_SR.DLYBS. Allows the start of QSCK to be delayed after the chip select has been asserted.
• The delay between consecutive transfers, programmed by writing QSPI_MR.DLYBCT.
  • If QSPI_MR.SMM = 0. Allows insertion of a delay between two consecutive transfers.
  • If QSPI_MR.SMM = 1. Allows insertion of a delay between last QSCK pulse and QCS rise.

These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time.