The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name:
AES_IMR
Offset:
0x18
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
SECE
PLENERR
EOPAD
TAGRDY
Access
R
R
R
R
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
URAD
Access
R
Reset
0
Bit
7
6
5
4
3
2
1
0
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 19 – SECE Security and/or Safety Event Interrupt
Mask
Bit 18 – PLENERR Padding Length Error Interrupt Mask
Bit 17 – EOPAD End of Padding Interrupt Mask
Bit 16 – TAGRDY GCM Tag Ready Interrupt Mask
Bit 8 – URAD Unspecified Register Access Detection Interrupt Mask
Bit 4 – TXBUFE Transmit Buffer Empty Interrupt Mask
Bit 3 – RXBUFF Receive Buffer Full Interrupt Mask
Bit 2 – ENDTX End of Transmit Buffer Interrupt Mask
Bit 1 – ENDRX End of Receive Buffer Interrupt Mask
Bit 0 – DATRDY Data Ready Interrupt Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
