33.4.1 Cache Operation

On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated with its configuration registers. The configuration interface is memory-mapped in the private peripheral bus.

Use the following sequence to enable the cache controller:

  1. Verify that the cache controller is disabled by reading the value of the CSTS (Cache Controller Status) bit of the Status register (CMCC_SR).
  2. Enable the cache controller by writing a one to the CEN (Cache Enable) bit of the Control register (CMCC_CTRL).
Important: When used as TCM, SRAM memories embedded in both cache controllers (CMCC0 and CMCC1) are 32-bit accessible memories only. 8-bit or 16-bit accesses are not allowed. The code to load the ITCM during application initialization must use a "32-bit wide" memory copy (memcpy) function.