14.1.2 Boot Sequence

Important:

Boot memory is always the ROM regardless of the value of GPNVM bits [8:5]. The ROM Code sets the Core 0 clock to 200 MHz on PLLB with a 12 MHz RC oscillator as input clock, only if the ROM code, via the configuration of the GPNVM bits, is instructed to start the SAM-BA monitor, the secure SAM-BA monitor, Secure boot with or without fall back to secure SAM-BA monitor.

Because the PMC is set up by the ROM code, care must be taken when the main application running from Flash sets a new clock configuration scheme for PLLB. Any switch of the input clock of the PLLB must avoid leading to an output frequency higher than 200 MHz. To avoid any potential over-clocking and provide more flexibility, Microchip software examples make use of the down-clocking feature for the ROM code available when programming GPBR15. For more information, see System Clock Tree.