24.3.1 GPBR Mode Register
This register is write-once. All bits are cleared at first power-up and on each loss of VDDBU.
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
| Name: | GPBR_MR |
| Offset: | 0x0 |
| Reset: | 0x00000000 |
| Property: | Read/Write-Once |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| GPBRRP15 | GPBRRP14 | GPBRRP13 | GPBRRP12 | GPBRRP11 | GPBRRP10 | GPBRRP9 | GPBRRP8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GPBRRP7 | GPBRRP6 | GPBRRP5 | GPBRRP4 | GPBRRP3 | GPBRRP2 | GPBRRP1 | GPBRRP0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GPBRWP15 | GPBRWP14 | GPBRWP13 | GPBRWP12 | GPBRWP11 | GPBRWP10 | GPBRWP9 | GPBRWP8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GPBRWP7 | GPBRWP6 | GPBRWP5 | GPBRWP4 | GPBRWP3 | GPBRWP2 | GPBRWP1 | GPBRWP0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – GPBRRPx GPBRx Read Protection
| Value | Description |
|---|---|
| 0 |
The content of the corresponding GPBR register (32-bit part-select) can be read. |
| 1 |
The corresponding GPBR register (32-bit part-select) always returns zero when read. |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – GPBRWPx GPBRx Write Protection
| Value | Description |
|---|---|
| 0 |
The corresponding GPBR register (32-bit part-select) can be written. |
| 1 |
The corresponding GPBR register (32-bit part-select) is write-protected. |