13.2.2.1 JTAG Debug Port (JTAG-DP) and Serial Wire Debug Port (SW-DP) Pins

The SWJ-DP is a combined JTAG-DP and SW-DP. SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by Arm.

At start-up, SWJ-DP pins are configured in SW-DP mode. SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP modes is performed through the PIO Controller Registers. Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations.

By default, the Serial Wire Debug Port (SW-DP) is active. If the debugger host wants to switch to the JTAG-DP, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the SWD-DP and enables the JTAG-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for instrumentation trace.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. The asynchronous trace can only be used with SW-DP, not JTAG-DP. The SWJ-DP pins are used for debug access to both cores.

The figure below illustrates the dual core debug implementation using only one SW-JTAG/SW-DP Debug Access Port. Star topology has been used to connect the AHB-AP 0 (Core 0) and AHB-AP 1 (Core) rather than legacy daisy-chaining method. Star topology provides higher performance than daisy-chain topology. This core debug architecture is fully supported by debug tools vendors.