Dual
Core Debugging with Serial Wire Debug Port (SW-DP) or JTAG Debug Port
(JTAG-DP) Debug Access Port Connected to Both Cores
Star
Topology AHB-AP Debug Access Port Implementation with common SW-DP / JTAG-DP
providing higher performance than daisy-chain topology.
Possibility
to Stop Each Core at a Debug Event on the Other Core (Hardware)
Possibility
to Restart Each Core when the Other Core has Restarted (Hardware)
Synchronization and Software Cross-Triggering with Debugger
Intrumentation Trace Macrocell (ITM) on Both Cores for Support of ‘printf’ Style
Debugging
Debug Access to All Memory and Registers in the System, including Cortex-M4 Register
Bank when the Core is Running, Halted, or Held in Reset
Flash Patch and Breakpoint (FPB) Unit for Implementing Breakpoints and Code
Patches
Data Watchpoint and Trace (DWT) Unit for Implementing Watchpoints, Data Tracing, and
System Profiling
IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
