22.5.9 Tamper Timestamping
The RTC can be used to stamp up to 5 tamper events. Tamper inputs are located on pins TMP0 to TMP4
As soon as a tamper is detected, the tamper event counter of the corresponding tamper input is incremented and the RTC stores the time of the day and the date of the tamper event in registers located in the backup area. The RTC stores the time, the date and the number of event of the first and the last tamper event on each TMP0 to TMP4 inputs.
In UTC mode, only the UTC time is stored. The date information is not relevant
The tamper counter saturates at 15. Once this limit is reached, the exact number of tamper occurrences since the last read of stamping registers cannot be known.
The time stamping on the TMPx input is enabled by setting the corresponding RTC_TAMPER.TAMPENx bit. The associated Low-power debouncer must be configured in the SUPC by writing a ‘1’ to the corresponding SUPC_WUMR.LPDBCENx and configuring the debouncing value in the corresponding SUPC_WUMR.LPDBCx field.
The first set of timestamping registers (RTC_FSTRx, RTC_FSDRx) cannot be overwritten, so once they have been written all data are stored until the registers are reset. Therefore these registers are storing the first tamper occurrence after a clear.
The second set of timestamping registers (RTC_LSTRx, RTC_LSDRx) is overwritten each time a tamper event is detected. Thus the date and the time data of the first and the second stamping registers may be equal. This occurs when the tamper counter value carried on field TEVCNT in RTC_LSTRx equals 1. Thus this second set of registers stores the last occurrence of tamper after a clear.
Reading a set of timestamping registers associated to a tamper input TMPx requires four accesses, one for the time of the day, one for the date and one for the tamper source.
Reading the RTC_LSDRx of a tamper input clears all content of the registers associated to this tamper input (RTC_FSTRx, RTC_FSDRX, RTC_LSTRx, RTC_LSDRx) and makes the timestamping registers available to store a new event.