27.10.1.1.1 Client Protection Types by Matrix
| Client | Peripheral | #hsel (8) | Mode | Max Size |
|---|---|---|---|---|
| 0 | SRAM0, port 0 |
0 @ 0x20000000 1 @ 0x20020000 2 @ 0x20040000 3 @ 0x20060000 | Internal Protected |
128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes |
| 1 | SRAM0, port 1 |
0 @ 0x20000000 1 @ 0x20020000 2 @ 0x20040000 3 @ 0x20060000 | Internal Protected |
128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes |
| 2 | SRAM0, port 2 |
0 @ 0x20000000 1 @ 0x20020000 2 @ 0x20040000 3 @ 0x20060000 | Internal Protected |
128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes |
| 3 | ROM | 0 @ 0x00000000 | Always User | 32 Kbytes |
| 4 | HS2LSASB (bridge to MATRIX1 host port 0) |
0 @ 0x04000000 0 @ 0x06000000 0 @ 0x40000000 0 @ 0x44000000 | Always User (1) |
32 Mbytes (QSPI Non-Cached) 32 Mbytes (AESB Non-Cached) 16 Mbytes (APB Bridge 0) 16 Mbytes (APB Bridge 2) |
| 5 | CPKCC |
0 @ 0x02020000 0 @ 0x02031000 | Internal Protected |
64 Kbytes (CPKCC ROM) 4 Kbytes (CPKCC RAM) |
| 6 | APB Bridge 3 | 0 @ 0x46000000 | Always User(2) | 16 Mbytes |
| 7 | HSAS2HSMSB (bridge to MATRIX2 host port 0) |
0 @ 0x48000000 0 @ 0x4A000000 0 @ 0x20080000 0 @ 0x20088000 | Always User(3) |
16 Mbytes (APB Bridge 1) 16 Mbytes (APB Bridge 4) 32 Kbytes (SRAM1, port 3) 16 Kbytes (SRAM2, port 3) |
| 8 | CMCCI/ITCM |
0 @ 0x11000000 0 @ 0x14000000 0 @ 0x16000000 1 @ 0x1FFFC000 | Always User(4) |
16 Mbytes (Flash Cached) 32 Mbytes (QSPI Cached) 32 Mbytes (AESB Cached) 16 Kbytes (ITCM) |
| 9 | CMCCD/DTCM |
0 @ 0x11000000 0 @ 0x14000000 0 @ 0x16000000 1 @ 0x1FFFA000 | Always User(4) |
16 Mbytes (Flash Cached) 32 Mbytes (QSPI Cached) 32 Mbytes (AESB Cached) 8 Kbytes (DTCM) |
| 10 | Flash |
0 @ 0x01000000 1 @ 0x01040000 2 @ 0x01080000 3 @ 0x010C0000 4 @ 0x01100000 5 @ 0x01140000 6 @ 0x01180000 7 @ 0x011C0000 0 @ 0x11000000 1 @ 0x11040000 2 @ 0x11080000 3 @ 0x110C0000 4 @ 0x11100000 5 @ 0x11140000 6 @ 0x11180000 7 @ 0x111C0000 0 @ 0xA1000000 1 @ 0xA1040000 2 @ 0xA1080000 3 @ 0xA10C0000 4 @ 0xA1100000 5 @ 0xA1140000 6 @ 0xA1180000 7 @ 0xA11C0000 | Internal Protected |
256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Non-Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Flash Cached) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) 256 Kbytes (Internal Flash Write) |
| 11 | HS2LSASB2 (bridge to MATRIX1 host port 1) |
0 @ 0x04000000 0 @ 0x06000000 | Always User(1) |
32 Mbytes (QSPI Cached) 32 Mbytes (AESB Cached) |
- Protection managed in MATRIX1.
- Protection managed in APB Bridge 3 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
- Protection managed in MATRIX2.
- Protection managed on final client (in MATRIX0 for Flash, in MATRIX1 for QSPI).
| Client | Peripheral | #hsel (4) | Mode | Max Size |
|---|---|---|---|---|
| 0 | QSPI |
0 @ 0x04000000 1 @ 0x04000000 2 @ 0x04000000 3 @ 0x04000000 0 @ 0x14000000 1 @ 0x14000000 2 @ 0x14000000 3 @ 0x14000000 0 @ 0x06000000 1 @ 0x06000000 2 @ 0x06000000 3 @ 0x06000000 | Scalable Protected |
32 Mbytes (QSPI Cached) 32 Mbytes (QSPI Cached) 32 Mbytes (QSPI Cached) 32 Mbytes (QSPI Cached) 32 Mbytes (QSPI Non-Cached) 32 Mbytes (QSPI Non-Cached) 32 Mbytes (QSPI Non-Cached) 32 Mbytes (QSPI Non-Cached) 32 Mbytes (QSPI Cached or Non-Cached through AESB) 32 Mbytes (QSPI Cached or Non-Cached through AESB) 32 Mbytes (QSPI Cached or Non-Cached through AESB) 32 Mbytes (QSPI Cached or Non-Cached through AESB) |
| 1 | AESB |
0 @ 0x16000000 0 @ 0x06000000 | Always User (1) |
32 Mbytes (QSPI Cached through AESB) 32 Mbytes (QSPI Non-Cached through AESB) |
| 2 | LS2HSASB (bridge to MATRIX0 host port 6) |
0 @ 0x01000000 0 @ 0x20000000 0 @ 0x20080000 0 @ 0x20088000 | Always User(2) |
16 Mbytes (Flash Non-Cached) 512 Kbytes (SRAM0 port 1) 32 Kbytes (SRAM1, port 3) 16 Kbytes (SRAM2, port 3) |
| 3 | APB Bridge 0 | 0 @ 0x40000000 | Always User(3) | 16 Mbytes |
| 4 | APB Bridge 2 | 0 @ 0x44000000 | Always User(4) | 16 Mbytes |
- Protection managed on final client QSPI in MATRIX1.
- Protection managed in MATRIX0.
- Protection managed in APB Bridge 0 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
- Protection managed in APB Bridge 2 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
| Client | Peripheral | #hsel (1) | Mode | Max Size |
|---|---|---|---|---|
| 0 | HSMS2HSASB (bridge to MATRIX0 host port 5) |
0 @0x20000000 0 @ 0x40000000 0 @ 0x46800000 | Always User (1) |
512 Kbytes (SRAM0, port 2) 16 Mbytes (APB Bridge 0) 8 Mbytes (APB Bridge 3, PMC) |
| 1 | HS2LSMSB (bridge to MATRIX3 host port 0) | 0 @ 0x48000000 | Always User(2) | 16 Mbytes (APB Bridge 1) |
| 2 | APB Bridge 4 | 0 @ 0x4A000000 | Always User(3) | 16 Mbytes |
| 3 | SRAM1, port 0 | 0 @ 0x00080000 | Internal Protected | 32 Kbytes |
| 4 | SRAM1, port 1 | 0 @ 0x00080000 | Internal Protected | 32 Kbytes |
| 5 | SRAM1, port 2 | 0 @ 0x20080000 | Internal Protected | 32 Kbytes |
| 6 | SRAM1, port 3 | 0 @ 0x20080000 | Internal Protected | 32 Kbytes |
| 7 | SRAM2, port 0 | 0 @ 0x00088000 | Internal Protected | 16 Kbytes |
| 8 | SRAM2, port 1 | 0 @ 0x00088000 | Internal Protected | 16 Kbytes |
| 9 | SRAM2, port 2 | 0 @ 0x20088000 | Internal Protected | 16 Kbytes |
| 10 | SRAM2, port 3 | 0 @ 0x20088000 | Internal Protected | 16 Kbytes |
- Protection managed in MATRIX0 for final client SRAM0 and in APB bridge 0 and APB bridge 3 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
- Protection managed in APB bridge 1 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
- Protection managed in APB Bridge 4 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).
| Client | Peripheral | #hsel (1) | Mode | Max Size |
|---|---|---|---|---|
| 0 | LS2HSMSB (bridge to MATRIX2 host port 1) |
0 @ 0x20000000 0 @ 0x20080000 0 @ 0x20088000 | Always User |
512 Kbytes (SRAM0, port 2) 32 Kbytes (SRAM1, port 3) 16 Kbytes (SRAM2, port 3) |
| 1 | APB Bridge 1 | 0 @ 0x48000000 | Always User | 16 Mbytes |
- Protection managed in MATRIX0 for final client SRAM0 and in MATRIX2 for final clients SRAM1 and SRAM2.
- Protection managed in APB bridge 1 (through the use of PPSELR registers, see MATRIX PPSELRx Register Descriptions).